1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a method for tightening the erase threshold voltage distribution in a flash Electrically Erasable Programmable Read-Only Memory (EEPROM).
2. Description of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block.
The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying, typically, 9 V to the control gate, 5 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 4 V.
The cell is read by applying typically 5 V to the control gate, 1 V to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 V), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 V), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying typically 12 V to the source, grounding the control gate and allowing the drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, a cell can be erased by applying a negative voltage on the order of -10 V to the control gate, applying 5 V to the source and allowing the drain to float.
A problem with the conventional flash EEPROM cell arrangement is that due to manufacturing tolerances, some cells become over-erased before other cells become erased sufficiently. The floating gates of the over-erased cells are depleted of electrons and become positively charged. This causes the over-erased cells to function as depletion mode transistors which cannot be turned off by normal operating voltages applied to their control gates, and introduces leakage during subsequent program and read operations.
More specifically, during program and read operations only one wordline which is connected to the control gates of a row of cells is held high at a time, while the other wordlines are grounded. However, a positive voltage is applied to the drains of all of the cells. If the threshold voltage of an unselected cell is zero or negative, leakage current will flow through the source, channel and drain of the cell.
This undesirable effect is illustrated in FIG. 1. The drains of a column of floating gate cell transistors T.sub.0 to T.sub.m are connected to a bitline BL, which is itself connected to a bitline driver 1. The sources of the transistors T.sub.0 to T.sub.m are typically connected to ground. One of the transistors T.sub.0 to T.sub.m is selected for a program or read operation by applying a positive voltage, e.g. 5 V, to its control gate which turns on the transistor. The control gates of the unselected transistors are connected to ground.
As viewed in FIG. 1, 5 V is applied to the transistor T.sub.1 which turns it on. A current I.sub.1 flows through the transistor T.sub.1 from ground through its source, channel (not shown) and drain and through the bitline BL to the driver 1. Ideally, the bitline current I.sub.BL should be equal to I.sub.1.
However, if one or more of the unselected transistors, e.g. the transistor T.sub.2 as illustrated in FIG. 1, is overerased, its threshold voltage will be zero or negative, and background leakage current will flow through the transistor T.sub.2 as indicated at I.sub.2. The bitline current I.sub.BL is now no longer equal to I.sub.1, but is equal to the sum of I.sub.1 and the background leakage current I.sub.2.
In a typical flash EEPROM, the drains of a large number, for example 512, transistor cells such as illustrated in FIG. 1 are connected to each bitline (column). If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline can exceed the cell read current. This makes it impossible to read the state of a cell on the bitline and renders the memory inoperative.
FIG. 2 illustrates how the threshold voltages of the cells or bits in a flash EEPROM can differ substantially from each other following an erase operation as shown by a solid line curve which represents the numbers of cells having particular values of threshold voltage V.sub.T. It will be seen that the least erased cells will have a relatively high threshold voltage V.sub.T MAX, whereas the most overerased cells will have a low threshold voltage which is below a minimum acceptable value V.sub.T MIN that can be negative. The characteristic illustrated in FIG. 2 is known as the threshold voltage distribution.
FIG. 3 illustrates how the background leakage current of a cell varies as a function of threshold voltage. The lower (more negative) the threshold voltage, the higher the leakage current. It is therefore desirable to prevent cells from being overerased and reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same high threshold voltage after erase on the order of 2 V.
It is known in the art to reduce the threshold voltage distribution by performing an overerase correction operation which reprograms the most overerased cells to a higher threshold voltage. This operation will result in the threshold voltage curve being altered to the shape indicated by broken line in FIG. 2 in which the threshold voltages of all of the cells are above the minimum acceptable value V.sub.T MIN. An overerase correction operation of this type is generally known as Automatic Programming Disturb (APD).
An APD method which is referred to as Automatic Programming Disturb Erase (APDE) is disclosed in U.S. Pat. No. 5,642,311, entitled "OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS", issued Jun. 24, 1997 to Lee Cleveland. The method includes sensing for overerased cells and applying programming pulses thereto which bring their threshold voltages back up to acceptable values.
A significant factor which results in an increase in the threshold voltage distribution is the source pull-up voltage which is applied to the sources of the cells during the erase pulses. As electrons are removed from the floating gates of the cells by Fowler-Nordheim tunneling through the tunnel oxide, the vertical electric field across the tunnel oxide decreases. The electric field at the beginning of erase must not be too high or it will adversely affect the tunnel oxide reliability and result in increased threshold voltage distribution.
The End-of-Erase (EOE) electric field at the completion of the erase operation must not be too low, or it will be insufficient to erase slow cells. However, it must not be too high, or it will cause overerasure of fast and typical cells in the main distribution.
It is known in the art to apply a main source drive voltage V.sub.SS to the sources of the cells through a pure resistive load. However, this expedient is limited in that the vertical electric field drops relatively sharply. If sufficient source voltage is applied to produce a suitable EOE field, the initial electric field will be too high. Conversely, if the source voltage is reduced to produce a suitably low initial electric field, the EOE field will be too low.
Another prior art expedient is to provide a source pull-up power supply including a constant current source. The object of this arrangement is to attempt to provide a constant electric field by maintaining the band-to-band tunneling current constant. However, the result is significant overerasure of fast and typical cells due to an excessively high EOE field.
FIG. 4 illustrates a composite source pull-up power supply 1 which includes a current source 2 and a load resistor R and represents an improvement over the pull-up supplies described above which include only a resistor or a constant current source. The current source 2 is connected to a main source supply voltage V.sub.SS.
A load line for the power supply 1 is illustrated in FIG. 5, which plots source current I.sub.S as a function of source voltage V.sub.S. If the current source 2 were omitted, the load line would include a downwardly slanting solid line portion 3 and a broken line portion 3'. The solid line portion 3 intersects the horizontal V.sub.S axis at the value V.sub.SS (open circuit) at which the current I.sub.S is zero. The broken line portion 3' intersects the vertical I.sub.S axis at a value V.sub.SS /R (short circuit), at which the current is maximum and the voltage V.sub.S is zero.
The current source 2 limits supplies a constant current of value I.sub.S MAX and limits the maximum voltage to V.sub.S MAX. The effect of the current source 2 is illustrated by a solid line curve portion 4 and a broken line curve portion 4'. Thus, for the power supply 1, the source voltage V.sub.S will increase along the curve portion 4 with the constant current I.sub.S MAX being supplied to the cell 1 until the curve portions 3 and 4 intersect at a voltage V.sub.S 1, and then increase with decreasing source current I.sub.S along the curve portion 3 to the limit value V.sub.SS.
The improvement provided by the current source 1 results from the current source 2 limiting or reducing the initial vertical electric field, and the resistor R helping to control the EOE field. However, not even the improved power supply 1 is able to provide an optimal vertical electric field throughout the entire erase operation, resulting in an undesirably large threshold voltage spread.
The problem is exacerbated by a phenomenon known as "cycling", in which the source voltage tends to increase as more erase pulses are applied to the cells. FIG. 6 illustrates the effect of cycling in which a curve 5 represents the threshold voltage increase without cycling. A curve 6 represents the threshold voltage characteristic at the end of erase due to the effect of cycling. It will be noted that the curve 6 is shifted upwardly from the curve 5, and that the source voltage V.sub.S becomes clamped to the limit value V.sub.SS along the curve 6 long before the cells have become completely erased.
The cycling phenomenon is caused by the generation of hot electron-hole pairs resulting from band-to-band tunneling. Whereas Fowler-Nordheim tunneling from the floating gate through the tunnel oxide layer to the source results in erasure of a cell, band-to-band tunneling also occurs between the substrate and the source. When a positive voltage is applied to the source junction with the control gate negative, a deep depletion region is formed underneath the gate-to-source overlap region. Electron-hole pairs are generated by the tunneling of valence band electrons into the conduction band. The electrons are collected by the source junction, and the holes are collected by the substrate.
Since the minority carriers (holes) generated thermally or by band-to-band tunneling in the source region flow to the substrate due to the lateral field near the Si--SiO.sub.2 interface, the deep depletion region remains present and the band-to-band tunneling can continue without creating an inversion layer. The generated holes gain energy because of the electric field in the depletion region. While the majority of these generated holes flow into the substrate, some of them gain sufficient energy to surmount the Si--SiO.sub.2 barrier and are trapped in the tunnel oxide layer.
The trapped holes reduce the horizontal electric field which results in reduced band-to-band tunneling current. This effect increases as the cells are cycled (progressively more erase pulses are applied thereto). Cycling results in exacerbation of the resistor and constant current source pull-up loads problems as described above. As the power supply 1 is a combination of a resistor and current source load, the individual problems associated therewith remain. There remains a substantial need in the art for a source pull-up power supply which provides a reduction in these undesirable effects and which can reduce the threshold voltage distribution of the erased memory.
It is also desirable to monitor the erase state of the memory in order to determine how far the erase operation has progressed and how many more erase pulses need to be applied. This information can be advantageously used to adjust the configuration of the pull-up power supply as erase progresses so that the applied electric field will be as close to optimal as possible.
As illustrated in FIG. 6, the main contribution to the source current V.sub.S is band-to-band tunneling (the Fowler-Nordheim tunneling current which causes the actual cell erasure is orders of magnitude lower), and this generally provides an accurate indication of the erase state. It is therefore at least theoretically possible to monitor the erase state of the memory by sensing the source current during the erase pulses (concurrent erase and verify).
However, in many applications the source voltage clamps to the maximum value V.sub.SS as indicated by the curve 6 and thereby provides no useful information relating to the erase state. For this reason, it is impractical in these applications to monitor the erase state by sensing the source voltage during the erase pulses. A further need exists in the art for an accurate method of determining the state of erasure of a flash EEPROM.